1. Field of the Invention
The present invention relates to a semiconductor apparatus and, more particularly, to a circuit that corrects variations in various elements in a semiconductor apparatus and variations in characteristics due to the variations in the elements.
2. Description of the Related Art
Examples of variations in elements of a semiconductor apparatus include variations in resistance or capacitance of a resistor or capacitor, threshold voltage Vt or ON-current of a transistor, base-emitter voltage Vbe of a bipolar transistor, resistance, capacitance, sensitivity or offset voltage of various sensor elements.
Variations in these elements cause characteristics of a circuit to change. For example, these characteristics include offset voltage, sensitivity, speed, output current, etc.
The following explanations will be focused on an infrared imaging device, but the present invention is applicable to any semiconductor apparatus capable of improving characteristics by correcting variations.
An example of a circuit that corrects variations in elements of a semiconductor apparatus is a semiconductor apparatus proposed in Japanese Patent Application Laid-Open No. 2000-114467 (hereinafter referred to as “Document 1”) by the inventor of the present invention. As shown in FIG. 19, this semiconductor apparatus includes a bolometer 1601 that converts incident infrared radiation to an electric signal, a transistor 1602 that applies a constant voltage to the bolometer 1601 and converts a resistance variation of the bolometer 1601 to a current variation, a capacitor 1603, one end of which is connected to the collector of the transistor 1602 and the other end of which is grounded, for integrating variations in the current that flows through the transistor 1602 and a variation correction circuit 1604 that corrects variations among a plurality of the bolometers 1601. The bolometers are arrayed two-dimensionally and bolometer signals corresponding to one column (V1 to Vn) in vertical direction are read by one reading circuit 1605 and all pixels are read by providing one reading circuit for each column (H1 to Hn). In FIG. 19, reference numeral 1609 denotes a bias circuit that supplies a bias voltage to a transistor of a cancellation circuit 1607, 1613 denotes a bias circuit that gives a bias to the bolometers and 1614 denotes a bias circuit that gives a bias voltage to the variation correction circuit 1604.
A certain reading circuit 1605 needs to correct and read variations of the bolometers of V1 to Vn and the variation correction circuit 1604 carries out corrections by changing its current value from one bolometer to another.
The variation correction circuit 1604 includes a plurality of current sources 1606 and current values of the current sources 1606 are arranged in binary form from MSB (most significant bit) to LSB (least significant bit) by sequentially changing two times each value. By changing current sources to be turned on by the bolometers 1601, it is possible to correct current variations due to resistance variations of the bolometers 1601.
Furthermore, an example of an imaging device disclosed in Japanese Patent Application Laid-Open No. 2000-004401 (hereinafter referred to as “Document 2”) includes reading circuits 1605 similar to those in FIG. 19, but corrects variations using the bias cancellation circuit 1607 instead of using the correction circuits 1604.
The bias cancellation circuit 1607 is usually used to cancel a bias component of a bolometer current and store only a signal component in a capacitor.
The imaging device disclosed in Document 2 configures resistance of this bias cancellation circuit 1607 (see FIG. 19) with a plurality of resistors that vary in binary form, thus allowing the bias cancellation circuit itself to have a variation correction function. That is, the bias cancellation circuit (bias current cancellation circuit) in Document 2 adopts a configuration comprising an FPN correction memory, a group of switches ON/OFF-controlled by digital data output from the FPN correction memory, one ends of which are commonly connected to a power supply and a group of resistors, one ends of which are connected to the other ends of the plurality of switches and the other ends of which are commonly connected to the collector of the transistor of the bias cancellation circuit 1607.
Furthermore, according to an example disclosed in Document 3 (“Low Cost 160×128 uncooled infrared sensor array”, SPIE Vol.3360 Part of the SPIE Conference on Infrared Readout Electronics IV April.1999), a bias voltage is supplied through a transistor to detect resistance variations of bolometers and variations in currents flowing through the bolometers are detected as a voltage by allowing an integrating circuit to integrate them using an operational amplifier. Then, the output of the integrating circuit is subjected to sample and hold. The integration operation and sample-and-hold operation are carried out by a plurality of reading circuits simultaneously. The proposal then describes that the sample-and-hold outputs of the respective reading circuits are multiplexed sequentially and output to the outside.
As shown in FIG. 20, according to the technique disclosed in above-described Document 3, a bolometer 1701 is connected to the source of a P-channel MOSFET (hereinafter referred to as “PchMOSFET”) 1702 through a switch and the gate of the PchMOSFET 1702 is connected to the output terminal of a digital/analog converter (hereinafter referred to as “D/A converter”) 1703. Furthermore, a bolometer 1705, which is thermally short-circuited, is connected to the source of an N-channel MOSFET (hereinafter referred to as “NchMOSFET”) 1704 and the gate of the NchMOSFET 1704 is connected to the output terminal of a D/A converter 1706. The connection point of the drain of the PchMOSFET 1702 and the drain of the NchMOSFET 1704 is connected to an integrator 1707 and a displacement current due to incident infrared radiation of the bolometer 1701 is converted to an integrated voltage by an integrating capacitor 1708.
Furthermore, an integrating circuit 1712 is constructed of the integrator 1707, the integrating capacitor 1708 and a reset switch 1709, and the integrating capacitor 1708 is periodically reset by the reset switch 1709. The integrator 1707 is made up of an OP amp (operational amplifier), the non-inverting input terminal of which is grounded and the inverting input terminal of which is connected to the input terminal of the integrating circuit 1712, with a parallel circuit of the capacitor 1708 and switch 1709 inserted between the inverting input terminal and a feedback path of the output terminal.
A sample-and-hold circuit (hereinafter referred to as “S/H circuit”) 1710 carries out sample and hold on the output voltage of the integrating circuit 1712 and multiplexer switches 1711 output the outputs of reading circuits 1713 to the outside sequentially. According to this document, there are nine reading circuits 1713.
However, the present inventor has noticed that the above-described conventional variation correction circuit has the following problems:
First, there is a trade-off between the area of the variation correction circuit and noise generated from the variation correction circuit. For example, in the example shown in above-described Document 1, current-related noise of the variation correction circuit is reduced as the resistance of the current source 1606 increases and the volume of the resistor increases. This is because:                The current-related noise of the resistor is inversely proportional to resistance.        The 1/f noise of the resistor is inversely proportional to the volume.        
There is normally a demand for making noise of the variation correction circuit smaller than noise of the bolometer and there is a need to increase the resistance of the current source 1606 and increase the volume of the resistor.
In addition, since there is also a need to sequentially increase the resistance in binary form from MSB to LSB twice at a time, the resistance of the LSB becomes extremely large, requiring a large area.
Second, there is a trade-off between power consumption and accuracy of correction. First, the example shown in above-described Document 1 requires another current that flows into the variation correction circuit 1604 in addition to the bolometer current. For this reason, further reduction of power consumption is preferred.
Furthermore, according to the configuration example described in above-described Document 1, the collector terminal of the current source 1606 (see FIG. 19) is connected to the capacitor 1603 and the collector terminal voltage changes together with an integration operation. For this reason, the current value of the current source 1606 varies subtly and it is susceptible to improvement in terms of linearity.
On the other hand, according to the example shown in FIG. 20 in above-described Document 3, since the drain of the transistor 1704 is controlled to a constant voltage by the operational amplifier 1707, there are few such problems, but there is a problem that power consumption of the D/A converters 1703 and 1706 that correct variations increases considerably.
Furthermore, the example shown in above-described Document 2 has relatively small current consumption but has a problem in terms of linearity as in the case of above-described Document 1.
Furthermore, the example of above-described Document 2 has a problem that the binary resistors arranged in parallel in the bias cancellation circuit cannot obtain sufficient accuracy of correction. Moreover, when resistors are used in series, there is also a problem that resistance becomes too small and the ON-resistance of switches, etc., grows to a noticeable level, failing to increase the accuracy of correction.
Third, the problems of the above-described area and power consumption make it difficult to apply the variation correction circuit to general LSIs such as a memory, cell-based IC and processor. With miniaturization technologies on the order of 100 nm in recent years, these LSIs have a problem that variations in threshold voltage Vt and ON-current of a transistor increase, which is accompanied by another problem that variations in an offset voltage of a sense amplifier or speed variations of a gate element become evident.
Therefore, it is a principal object of the present invention to provide a semiconductor apparatus capable of realizing a high accuracy variation correction function with low power consumption, low noise and a small area.